A computer system typically uses variety of digital integrated circuits (ICs). For example, desktop computer systems commonly include digital ICs to implement user interfaces for receiving user instructions and handling the electronic processing of those instructions. As the complexity of the implementation increases, the system of digital ICs becomes more sophisticated. In turn, as digital devices become more sophisticated, the task of designing, testing, and debugging the digital systems implementing the devices becomes more difficult. Thus, validation of a system design and verification of the proper functionality of the system has become an important factor in the development of computer technology.
Mechanisms to observe the sequential logic state of a digital IC on a tester, or in a system, are critical to debugging operations. The observation is typically achieved when the IC is exercising its intended functionality on the tester or the system. To observe the logical state of any digital IC, the state elements need to have scan capability. Scan capability refers to the inclusion of an alternative path used to control and/or observe the state of a state element. With various types of scan capability and global scan architecture, there are three fundamental ways of observing logic state of a digital IC: shadow scan, dumping state, and single stepping.
In the shadow scan, key state elements to be observed are “shadowed” in scannable state elements and the scanned information is shifted out serially in real time without stopping the functional clock of the IC. In the dumping state, at a predetermined clock cycle during the operation of the IC, the functional clock signal is stopped. Then, the state is latched in the slave portions of the state elements and is serially shifted out for observation. In the single stepping, at every clock step, the functional clock signal is stopped, the state is latched in the slave portions of the state elements, and is shifted out for observation. Also, the state information is shifted back in to restore the state of the machine to what it was when the clock stopped. Once the shifting out and shifting in are completed, the functional clock is re-started.
There are various test design strategies, know as design-for-testability (DFT) techniques for ensuring the ratio of the number of passed ICs to the total number of tested ICs is high. In DFT, test patterns may be generated using an automatic test pattern generation (ATPG) algorithm to be applied via chip pins or scan mechanism. Scan capability refers to the inclusion of an alternative path used to control and/or observe the state of a state element.
Scan-based ATPG is a method of testing digital circuits for manufacturing defects. In this method, a state element, e.g., flip-flop or latch, in the circuit is modified to give controllability and observability of the state of the element using a sequential path that can switch between test operation (test mode) and evaluative operation (normal mode).
Two scan-based algorithms are combinational and sequential ATPG. Combinational ATPG is when all state elements in the design have scan capability. In combinational ATPG, all state elements can be controlled to a known state in test mode. The combinatorial logic between state elements can be evaluated in one clock cycle and the result latched in the state elements. Sequential ATPG is when only some of the state elements in the design have scan capability. In sequential ATPG, only those elements that have scan capability can be controlled to a known state in scan mode. The combinatorial logic between state elements and non-state elements are evaluated over multiple clock cycles and the results are stored in the scan capable elements.
Typically, flip-flops in digital circuits are single edge-triggered. These flip-flops latch state either on the positive (0 to 1 transition) of the clock or on the negative edge (1 to 0 transition). A faster data rate and some power savings can be achieved if the state element is designed such that it latches the state on the positive as well as the negative edge of the clock. This type of flip-flop that latches on both the positive edge and negative edge of the clock is known as a dual edge-triggered flip-flop.
Referring to FIG. 1, a dual edge-triggered flip-flop (10) is shown. As can be seen, the dual edge-triggered flip-flop has an input (D), an output (Q), and receives a clock signal (CLK). At the positive edge of the clock signal (CLK), the input (D) is sent to the output (Q). Also, at the negative edge of the clock signal (CLK), the input (D) is sent to the output (Q). Those skilled in the art will appreciate that while a D flip-flop is used as the exemplary flip-flop throughout this specification. The present invention is equally applicable to any dual edge-triggered flip-flop.
Referring to FIG. 2, a circuit diagram of the dual edge-triggered flip-flop (10) is shown. Essentially, the flip-flop (10) includes two latches (12) and (14). These latches (12) and (14) are each a pair of cross-coupled inverters. Transmission gates (16) and (18) are coupled around latch (12) and receive the complement of the clock signal ({overscore (CLK)}) and the clock signal (CLK) respectively. Likewise, transmission gates (20) and (22) are coupled around latch (14) and receive the clock signal (CLK) and complement of the clock signal ({overscore (CLK)}) respectively. The transmission gates may be pairs of a P-type Metal Oxide Semiconductor (P-MOS) and an N-type Metal Oxide Semiconductor (N-MOS). Thus, on the positive edge of the clock signal, the data (D) latched in latch (12) is sent to output (Q) and on the negative edge of the clock signal, the data (D) latched in latch (14) is sent to output (Q).